memory array 1024 x 1024 row select i/o circuit pre-charge circuit column select data cont data cont vcc vss a10 a11 a12 a13 a14 a15 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 - i/o8 i/o9 - i/o16 we oe bhe ble ce 1 2 3 12 10 11 8 39 13 9 7 6 4 5 26 25 24 2322 21 14 15 16 17 18 19 20 40 41 42 43 44 38 37 36 35 34 33 32 31 30 29 28 27 a9 a8 a7 a6 a5a4 a3 a2 a1 we i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 a0 ce v ss vcc nc a15 a14 a13 a12 a11 a10 i/o16 i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 nc nc vss vcc bhe ble oe v 62 c 1 1 6 102 4 l (l) ultra low power 64k x 16 cmos sram features ? u ltra low-power consumption - active: 30ma i cc at 70ns - stand-by: 5 m a (cmos input/output) 1 m a ( cmos input/output, l version) ? 70/85/100/120 ns access time ? equal access and cycle time ? single +1.8v to 2.2v power supply ? tri-state output ? automatic power-down when deselected ? multiple center power and ground pins for improved noise immunity ? individual byte controls for both read and write cycles ? available in 44 pin tsop (ii) package functional description the v 62 c1 1 6 10 24 l is a low power cmos static ram o rg a nized as 65,536 words by 16 bits. easy memory exp - a n si on is provided by an active low ( ce ) and ( oe ) pin. this device has an automatic power-down mode feature when deselected. separate byte enable controls ( ble and bhe ) allow individual bytes to be accessed. ble controls the lower bits i/o1 - i/o8. bhe controls the upper bits i/o9 - i/o16. writing to these devices is performed by taking chip enable ( ce ) with write enable ( we ) and byte enable ( ble / bhe ) lo w . reading from the device is performed by taking chip enable ( ce ) with output enable ( oe ) and byte enable ( ble / bhe ) low while write enable ( we ) is held high. tsop(ii) logic block diagram r e v . 1 . 1 ap ri l 2001 v62 c 1 16 10 24 l ( l) 1
v 62 c 1 16 10 24 l( l ) absolute maximum ratings * * note: stresses greater than those listed above absolute maximum ratings may cause permanent damage to the device. this is a stress ra t- ing only and function operation of the device at these or any other conditions outside those indicated in the operational sectio ns of this spec- ification is not implied. exposure to a bsolute m aximum r ating conditions for extended periods may affect reliabilit y . parameter symbol minimum maximum unit voltage on any pin relative to gnd vt -0.5 +4.0 v power dissipation pt - 1.0 w storage t emperature (plastic) tstg -55 +150 0 c temperature under bias tbias -40 +85 0 c truth table * key: x = don?t care, l = lo w , h = high ce oe we ble bhe i/o1-i/o8 i/o9-i/o16 power mode h x x x x high-z high-z standby standby l l h l h data out high-z active low byte read l l h h l high-z data out active high byte read l l h l l data out data out active word read l x l l l data in data in active word write l x l l h data in high-z active low byte write l x l h l high-z data in active high byte write l h h x x high-z high-z active output disable l x x h h high-z high-z active output disable 2 recommended operating conditions (t a = 0 o c to +70 o c / -40 o c to 85 o c**) * v il min = -2.0v for pulse width less than t rc /2. ** for industrial temperature parameter symbol min typ max unit v cc 1.8 2.0 2.2 v gnd 0.0 0.0 0.0 v v ih 1.6 - v cc + 0.2 v v il -0.5* - 0.4 v supply voltage input voltage r e v . 1 . 1 ap ri l 2001 v62 c 1 16 10 24 l ( l)
ac test conditions input pulse level 0.4v to 1.6v input rise and fall time 5ns input and output timing reference level 1.0v output load condition 70ns/85ns c l = 30pf + 1ttl load load for 100ns/120ns c l = 100pf + 1ttl load c l * figure a. * including scope and jig capacitance ttl v 62 c 1 16 102 4 l ( l ) dc operating characteristics (v cc = 2v + 10%, gnd = 0 v , t a = 0 0 c to +70 0 c / -40 0 c to 85 0 c) input leakage current i i li v cc = max, v in = gnd to v cc - 1 - 1 - 1 - 1 m a output leakage current i i lo ce = v ih or v cc = max, v out = gnd to v cc - 1 - 1 - 1 - 1 m a operating power supply current i cc ce = v il , v in = v ih or v il , i out = 0 - 3 - 3 - 3 - 3 ma average operating current i cc1 i out = 0ma, min cycle, 100% duty - 30 - 25 - 20 - 20 ma i cc2 ce < 0.2v i out = 0ma, cycle time=1 m s, duty=100% - 3 - 3 - 3 - 3 ma standby power supply current (ttl level) i sb ce = v ih - 0.5 - 0.5 - 0.5 - 0.5 ma standby power supply current (cmos level) i sb1 ce > v cc - 0.2 v l v in < 0.2v or v in > v cc - 0.2v l l - 5 1 - 5 1 - 5 1 - 5 1 m a m a output low v oltage v ol i ol = 2 ma - 0.4 - 0.4 - 0.4 - 0.4 v output high v oltage v oh i oh = -1 ma 1.6 - 1.6 - 1.6 - 1.6 - v -70 -100 -120 unit parameter sym t est conditions min max min max min max min max -85 3 capacitance (f = 1mhz, t a = 25 0 c) parameter* symbol t est condition max unit input capacitance c in v in = 0v 7 pf i/o capacitance c i/o v in = v out = 0v 8 pf * this parameter is guaranteed by device characterization and is not production tested. r e v . 1 . 1 a pr il 2001 v62 c 1 16 10 24 l ( l) - - - -
v 62 c 1 161 02 4l ( l ) parameter sym unit note read cycle time t rc 70 - 85 - 100 - 120 - ns address access time t aa - 70 - 85 - 100 - 120 ns chip enable access time t ace - 70 - 85 - 100 - 120 ns output enable access time t oe - 40 - 40 - 50 - 60 ns output hold from address change t oh 10 - 10 - 10 - 10 - ns chip enable to output in low-z t lz 10 - 10 - 10 - 10 - ns 4,5 chip disable to output in high-z t hz - 30 - 35 - 40 - 40 ns 3,4,5 output enable to output in low-z t olz 5 - 5 - 5 - 5 - ns output disable to output in high-z t ohz - 25 - 30 - 35 - 40 ns ble , bhe enable to output in low-z t blz 5 - 5 - 5 - 5 - ns 4,5 ble , bhe disable to output in high-z t bhz - 25 - 30 - 35 - 40 ns 3,4,5 ble , bhe access time t ba - 40 - 40 - 50 - 60 ns read cycle (9) (v cc = 2v + 0.2 v , gnd = 0 v , t a = 0 0 c to +70 0 c / -40 0 c to +85 0 c) write cycle (11) (v cc =2v + 0.2 v , gnd = 0 v , t a = 0 0 c to +70 0 c / -40 0 c to +85 0 c) parameter symbol unit note write cycle time t wc 70 - 85 - 100 - 120 - ns chip enable to write end t cw 60 - 70 - 80 - 90 - ns address setup to write end t aw 60 - 70 - 80 - 40 - ns address setup time t as 0 - 0 - 0 - 0 - ns write pulse width t wp 50 - 60 - 70 - 80 - ns write recovery time t wr 0 - 0 - 0 - 0 - ns data valid to write end t dw 30 - 35 - 40 - 45 - ns data hold time t dh 0 - 0 - 0 - 0 - ns write enable to output in high-z t whz - 30 - 35 - 40 - 40 ns output active from write end t ow 5 - 5 - 5 - 5 - ns ble , bhe setup to write end t bw 60 - 70 - 80 - 90 - ns min max min max min max min max -70 -85 -100 -120 4 min max min max min max min max -70 -85 -100 -120 r e v . 1 . 1 ap ri l 2001 v62 c 1 16 10 24 l ( l)
timing waveform of read cycle 1 (address controlled) t rc t aa t o h data valid address data out timing waveform of read cycle 2 t ohz t rc t olz t ace t lz(4,5) ce previous data valid address t oh t aa t oe t ba t blz(4,5) t bhz(3,4,5) t hz(3,4,5) (ble/bhe) oe data out data valid high-z v 62 c 1 16 10 24 l ( l ) 5 notes (read cycle) 1. we are high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition referenced to v oh or v ol levels. 4. at any given temperature and voltage condition t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured + 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 6. device is continuously selected with ce = v il . 7. address valid prior to coincident with ce transition lo w . 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. for test conditions, see ac test condition , figure a. r e v . 1 . 1 ap ri l 2001 v62 c 1 16 10 24 l ( l)
v 62 c1 1 61 02 4l ( l ) timing waveform of write cycle 1 (address controlled) timing waveform of write cycle 2 (ce controlled) timing waveform of write cycle 3 (ble/bhe controlled) address high-z t dw t dh t wp (2) t wc t cw (3) t aw t wr (5) t as (4) address address data in data in data in data out data out data out ce ce ce ble/bhe ble/bhe ble/bhe we we we t bw t lz t blz t whz (6) high-z (8) high-z t whz (6) high-z (8) high-z high-z t dw t dh t wp (2) t bw t as (4) t wr (5) t cw (3) t aw t wc high-z high-z (8) t ow t ohz (6) t dw t dh t wp (2) t bw t as (4) t cw (3) t aw t wc t wr (5) 6 r e v . 1 . 1 a pri l 2001 v62 c 1 16 10 24 l ( l)
v 62 c 1 16 10 24 l ( l ) 7 notes (write cycle) 1. all write timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low ce and we . a write begins at the latest transition among ce and we going low: a write ends at the earliest transition among ce going high and we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of ce going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. 6. if oe , ce and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occu r . 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. if ce goes low simultaneously with we going low or after we going lo w , the outputs remain high impedance state. 9. d out is the read data of the new address. 10. when ce is low: i/o pins are in the outputs state. the input signals in the opposite phase leading to the output should not be applied. 11. for test conditions, see ac test condition , figure a & b. r e v . 1 . 1 a pr il 2001 v62 c 1 16 10 24 l ( l)
v 6 2 c 1 16 102 4 l ( l ) 8 notes 1. l-version includes this feature. 2. this parameter is sample d and not 100% tested. 3. for test conditions, see ac test condition , figure a. 4. this parameter is tested with cl = 5pf as shown in figure b. transition is measured + 500mv from steady-state voltage. 5. this parameter is guaranteed, but is not tested. 6. we is high for read cycle. 7. ce and oe are low for read cycle. 8. address valid prior to or coincident with ce transition lo w . 9. all read cycle timings are referenced from the last valid address to the first transtion address. 10. ce or we must be high during address transition. 11. all write cycle timings are referenced from the last valid address to the first transition address. data retention mode v dr > 1.0v vcc_typ v ih v ih v dr v cc ce t r t cdr vcc_typ data retention waveform (l v ersion only) ( t a = 0 0 c to +70 0 c / -40 0 c to +85 0 c) data retention characteristics (l v ersion only) (1) parameter symbol t est condition min max unit v cc for data retentio n v dr ce > v cc - 0.2v 1.0 - v data retention current i ccdr l - 5 1 m a chip deselect to data retention time t cdr v in > v cc - 0.2v or 0 - ns operation recovery tim e (2) r v in < 0.2v t rc - ns r e v . 1 . 1 ap ri l 2001 v62 c 1 16 10 24 l ( l) t
ordering information device type* speed package v 62 c 1 16 10 24 l -70 t 70 ns 44-pin tsop type 2 v 62 c 1 16 10 24 l -85 t 85 ns v 62 c 1 1 6 1 02 4 l -100 t 100 ns v 62 c1 1 610 24 l -120 t 120 ns v 62 c1 1 6 102 4 l l -70 t 70 ns v 62 c 1 1 61 02 4 l l -85 t 85 ns v 62 c1 1 61 02 4l l -100 t 100 ns v 62 c1 1 610 24 l l -120 t 120 ns 9 * for indu s trial temperature tested devices, an ?i? designator will be added to the end of the device numbe r . r e v . 1 . 1 ap ri l 2001 v62 c 1 16 10 24 l ( l) v 62 c 1 16 10 24 l( l )
mosel vitelic w orld wide offices ?co p y r ight 2001, mosel vitelic inc. 4 /01 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u .s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-826-6176 fax: 214-828-9754 v 6 2 c 1 16 10 24 l (l )
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